KB: Validate transmission impedance computed in layer stack

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Transmission impedance calculated in the layer stack may differ from results provided by third-party calculators or tools, requiring validation. The discrepancy arises from the fundamental difference between web calculators, which rely on closed-form expressions, and Altium's Layer Stack Manager. The latter utilizes Simbeor's 2D quasi-static field solver based on the Method of Moments. This approach is rigorously validated through convergence tests, comparisons, and measurements. To account for differences, review detailed settings such as 'Use Surface Finish' and 'Use Solder Mask' in the Layer Stack Manager, as they can impact results compared to web calculators. Additionally, ensure parameters like the reference plane are not overlooked. To avoid potential issues, consult your board fabricator and opt for oversized estimates for trace width and gap, providing flexibility for modifications later.

Solution Details

You can read more here:
The Simbeor SFS
https://forum.live.altium.com/#/posts/249000/783549

Additionally, options such as 'Use Surface Finish' and 'Use Solder Mask' in Layer Stack Manager could attribute to the difference from a web calculator result, typically without such consideration.

Another frequently overlooked parameter is the reference plane. If unspecified for the Coplanar configuration, Altium assumes that it is on the same layer as the signal, with S (clearance) being the only dependent parameter associated with adjacent conductors.
Support for Coplanar Transmission Line Structures

If you also have no reference on each side of the routing, then theoretically, this is not coplanar, i.e., "impedance controlled;" it is just differential pair routing. Ultimately, you could consider adjusting the spacing "S" to the ground shielding to a significantly large value. If you are making these types of adjustments, you should consider any possible ramifications from those settings.

Here is another paper comparing web calculators and Simbeor SFS integrated into Layer Stack Manager since its inception in 2020:
Impedance Calculation

The bottom line, however, is that it is best that you consult your board fabricator upfront, and when in doubt, try to stay with an oversized estimation for trace width/gap so that you have room in your board later to narrow them after you solidify the spec with your fabricator. Here is another forum thread on the topic discussed among other expert users:
https://forum.live.altium.com/#/posts/251714/798646

It is also worth mentioning that the convenient command Retrace allows you to update the existing trace width/gap of an obsolete impedance profile in one go.
 

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